WALTA Test Stand Electronics

(... always under construction ...)

WALTA Test Station at NPL
WALTA Test Station at NPL

Block Diagram

Note: Yellow blocks mean NIM modules and green are VMEbus modules. Other colors indicate independent units.

Short summary of the circuit:

Currently, 3 photo-multiplier tubes (PMT) are connected to the test station. A High Voltage (HV) supply provides high voltages for each PMT. The analog PMT signals are amplified via a Phillips Scientific 740 NIM module, which consists of 4 Linear/Logic Fan-In/Out channels, 3 of which are used for the PMTs (1 each). Each Fan-In/-Out channel provides 2 outputs. The PMT signals are then processed in two parallel stages:
  1. Trigger Generation:

    The analog PMT signals go through a discriminator unit (LeCroy 821). A discriminator generates a digital output (either ON or OFF) if the analog input signal is below a certain threshold level, which can be adjusted on the front panel of the module. The digitized signals are then processed in 2 coincidence (AND gates) channels (LeCroy 465). One coincidence channel requires all 3 PMTs to have a pulse at the same time (3-fold coincidence) to generate an output pulse, whereas the second channel only requires 2 PMTs (here: 1 and 3) for an output pulse (2-fold coincidence). The coincidence pulses are counted by a separate counter for each of the two concidence levels. And one of the coincidence channels is used as a trigger signal for the DAQ system (here: 3-fold).

  2. Data Acquisition (DAQ):

    A digital delay pulse generator (SRS DG535) provides precision timing pulses for the DAQ system from the trigger signal:

    A Charge-to-Time (QTC) module converts the charge (Q) of each analog PMT pulse into a digital variable-width pulse. The width of each output pulse is linearily proportional to the charge of an input pulse below a settable threshold level (see QTC specification).

    The QTC outputs are connected to a Time-to-Digital Converter (LeCroy model 1176) via differential (dECL level) twisted-pair cables. The TDC records leading and trailing edges of the digitized QTC pulses with 1 nanosecond resolution in a circular buffer. If a "Common Stop" (CM) pulse is issued (here: 4 µsec delayed trigger signal) then the circular buffer is stopped and its contents are converted for VME readout into a so-called "Event" buffer (see TDC info). During the conversion time, the TDC cannot process any QTC pulses, and the "BUSY" output is set HIGH (= "deadtime" = approx. 1.25 ... 20 µsec, depending on number of QTC pulses to be converted).

    A home-made Local Time Clock module module records trigger times and TDC busy flags into a FIFO buffer for VME readout. It also records absolute high-precision time-of-day via an integrated Global Positioning System (GPS) receiver.

    The VME modules are controlled and read out via a PCI-to-VMEbus bridge adapter (Bit3/SBS 616) by a Linux PC box, running custom-made DAQ software.

Data Sheets

Custom-made Electronics Data Sheets:

Note: The LTC and QTC modules were originally developed for Super-Kamiokande and K2K).

Commercial Electronics Data/Product Sheets:

Software

Links

HGB, last update Fri Jun 22 07:40:58 PDT 2001