Proposal for the air shower readout board (Qnet II)
It turns out that the TMC (Time Memory Cell) TDC chip from KEK that
we use in the muon system at D0 will of itself meet the requirements as
outlined during the Friday palaver. It will measure the time of both edges
of an incoming signal which gives you the time over threshold time that
you had initially talked about. The chip has four channels and can be
operated with a bin width of 640ps with its clock operating at 50MHz,
which you had said was sufficient resolution. For detailed information on
this chip see:
http://research.kek.jp/people/araiy/TEG3/TMC304manual.pdf
After a quick inventory I have found 74 salvageable chips which are
at present mounted on some mix of prototype and damaged D0 hardware. In
addition there are of order 800 spare TMCs for a 5000 chip system. Our
failure rate to date has been 2 chips. Hans has made inquiries to Japan
about buying more of these chips beyond the 100 or so that we could
probably beg from D0.
The logic downstream of the TMC would be more complex. A data buffer would
be required. The cost of a "small" Altera FPGA with sufficient logic to do
this job is about $15.00 (+ $2.00 for the configuration prom). With this
chip we can do all the scalers including the local time clock and buffer
multiple events in hardware, so there would be no trigger deadtime. The
signal chain on the board is straightforward. Amp/Disc to TMC to FPGA to
uC. The mounting and control of the GPS daughter card would be as we
talked about on Friday.
Additional real estate on this board as compared to the present board
would be required for the GPS daughter card (51x83mm), a larger logic chip
(30x30mm instead of 13.2x13.2mm) and the TMC chip (22.6x22.6mm). Chips can
be mounted under the GPS daughter card if necessary. The board can be
approximately same size as the one we already have.
Additionally D0 has on hand about 1100 unused 20MSPS video ADC chips. If a
charge measurement were desired in place of the time over threshold,
An integrator and this ADC would form a charge measurement channel.
We are basically ready to make a schematic of most of the parts of
the board. We need to think a little bit about the details of the
temperature and pressure sensor. We have now freed up all the ADC channels
of the microcontroller for instrumentation.
The approximate cost for the board would be less than $400 each for
quantity 50.
Assuming 20% of Hans' time available to work on this..
Timeline/division of labor:
- Study of sensors - 1 week (FNAL)
- Concurrent with drawing the schematic - 2 weeks (FNAL)
- Board layout - 4..5 weeks (UW)
- Logic equations - 4..5 weeks (UW/FNAL)
- Letting board fab contract - 1 week
- Board fab - 5..10 working days
(How many prototypes 5..10?)
- Assembly - 1 week (FNAL)
- (C software - 1 month (FNAL / ???)
- Enough firmware to evaluate board performance,
No fancy stuff
- Board evaluation - 3 months (FNAL/UW/UNL)
submitted 11/14/2001 by
Sten Hansen /
Hans Berns